Scaling CMOS can only be enabled with fundamental architecture innovations both at device level as well at the SoC level. At the device level we see the track height scaling trend continue, fueled by novel devices such as Forksheet and its extension to VHV, CFET and 2D channel devices. In parallel, system-level innovations leading to memory partitioning and backside interconnect are needed to maintain SoC scaling.
Geert Hellings received his Ph.D. degree at the Electrical Engineering Department (ESAT), of KU Leuven, Belgium on the integration of advanced field effect transistors with high-mobility channel materials and heterostructure confinement for digital logic applications. In 2011, he joined the Device Reliability and Electrical Characterization group in imec, where he worked on I/O, ESD and Latchup in advanced LOGIC Technologies. Since 2020, he is the Program Manager for the Logic Insite Program at imec, focusing on Design-Technology Co-Optimization and the Logic Roadmap. He holds 20+ patents and has authored or co-authored approximately 200 technical papers for publication in journals and presentations at conferences.