Moving from monolithic to the second and third dimension is becoming increasingly important within the semiconductor industry. Heterogeneous and chiplet integration have increased in complexity over the years as well as in the number of options available. The vision of improving the device efficiency and system computing and communication performance drives the approach toward 3D integration, whereas the need for finer RDL line/spacing as well as smaller micro-bump and micro-pillar critical dimensions delineate integration design rules at the package, wafer level and substrate level too. A profound evaluation of resists typically used in advanced packaging processes is shown in this work with the aim of employing a digitally driven maskless exposure method and presenting its dynamic patterning performance capability with respect to the heterogeneous integration requirements fulfilling fine 2/2µm L/S. Nevertheless, the importance of design flexibility and the ability not only to adopt both die- and wafer-level designs simultaneously but also the viability of fast tapeout changes is addressed.
Bozena Matuskova is business development manager at EV Group, where she is focused on advanced packaging market, especially lithography solutions including maskless exposure, precision mask alignment and resist processing systems. Bozena holds a master’s degree in Microelectronics from Slovak University of Technology and has 8+ years of professional experience in engineering, business development and technical product marketing activities, in both semiconductor & automation engineering industry.